Single data rate (SDR) synchronous DRAM integrated circuits have been developed in order to improve the performance of conventional dynamic random access memory (DRAM) integrated circuits. In additional, double data rate (DDR) synchronous DRAM integrated circuits have been developed in order to improve the performance of single data rate synchronous DRAM integrated circuits. Single data rate synchronous DRAM integrated circuit devices process one data value during one period of a clock signal. Double data rate synchronous DRAM integrated circuits process two data values during one period of a clock signal. Therefore, the double data rate synchronous DRAM integrated circuit can have a data processing speed twice as high as that of the single data rate synchronous DRAM integrated circuit.
Because the double data rate synchronous DRAM integrated circuit has a very high data processing speed, the performance of the double data rate synchronous DRAM integrated circuit typically cannot be tested with low speed data equipment. For example, the operating frequency of the double data rate synchronous DRAM integrated circuit presently is about 100 MHz and the operating frequency of conventional test equipment for testing a wafer on which DRAM integrated circuits are arranged presently is only about several MHz (e.g., 5 MHz). Also, since the double data rate synchronous DRAM integrated circuit has a specific pin called a data strobe, the double data rate synchronous DRAM integrated circuit typically can only be tested by enabling the data strobe pin from the outside. Since conventional test equipment typically does not have the capability of enabling the data strobe pin, double data rate synchronous DRAM integrated circuits typically cannot be tested with conventional test equipment. Thus, notwithstanding the advantages of double data rate SDRAM deices, there continues to be a need for improved techniques to test such devices using conventional test equipment.